This invention relates generally to digital circuits, and more particularly, to a digital circuit for converting first and second speed-proportional pulse trains which are phase-shifted with respect to one another, into a speed-proportional pulse train having a frequency which is four times that of the first and second pulse trains, and a sign signal indicative of the direction of rotation.
Commercially available tachometers are generally arranged to deliver two pulse signal channels, each having a frequency which is proportional to the speed of rotation. Ideally, the pulse trains are phase-shifted by 90.degree.; the pulse trains either leading or lagging one another depending upon the direction of rotation. It is desirable to base the speed measurement on a frequency which is as high as possible, thereby enabling the evaluation to be made by means of a smoothing capacitor which has a relatively small capacity compared to a capacitor which would be required at a lower frequency. In this manner, the smaller capacitor can achieve a ripple characteristic similar to that of the larger capacitor operating at a lower frequency, while enabling the time constant to remain small. In addition, the higher signal frequency permits the indication of the digital evaluation to follow more quickly the actual speed value. In commercially available evaluation circuits, a high evaluation frequency is obtained by releasing in both channels an evaluation pulse for every positive-going and negative-going flank, thereby producing a pulse train with four times the frequency of the pulse train in the two pulse channels. The direction of rotation is ascertained by determining whether the phase shift is positive or negative.
High resolution is obtained for low speeds by using transmitters having a high number of pulses per revolution. When using such transmitters, the output signals for high speeds are of correspondingly high frequency, illustratively on the order of approximately 120 kHz. Such high frequency operation emphasizes the effects of unavoidable asymmetries in the pickup and different propagation times in the electronic processing. Thus, at high frequencies, it is not assured whether the pulses of the two pulse channels have a 90.degree. phase relationship. In addition, since changes in the logical states in both channels occur very quickly, and the logic circuitry may be of the C-MOS type having a maximum processing speed of approximately 1 MHz, there is a danger that the logic state changes may not processed at such high frequencies. Faulty evaluation results if the time between two changes in both pulse channels becomes shorter than the length of the evaluation pulses of the evaluation circuit which are released with every pulse flank. The permissible frequency of the pulse trains delivered by the tachometer is therefore limited by the width of the evaluation pulses, and therefore the consequence of all worst-case tolerances must be considered.
In addition to the foregoing, difficulties are encountered if the pulse train generated by the evaluation circuit is processed in a clock-controlled circuit, such as in a computer, because the pulse train cannot be synchronized with the clock frequency.
It is, therefore, an object of this invention to provide an evaluation circuit of the type wherein the speed-proportional pulse train is synchronized with a clock pulse raster so that the circuit operates without a frequency limit.